-------------------------------------------------------------------------------
-- system_core1_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library core1_v1_00_a;
use core1_v1_00_a.all;

entity system_core1_0_wrapper is
  port (
    S_AXI_ACLK : in std_logic;
    S_AXI_ARESETN : in std_logic;
    INTERRUPT : out std_logic;
    S_AXI_AWADDR : in std_logic_vector(31 downto 0);
    S_AXI_AWVALID : in std_logic;
    S_AXI_AWREADY : out std_logic;
    S_AXI_WDATA : in std_logic_vector(31 downto 0);
    S_AXI_WSTRB : in std_logic_vector(3 downto 0);
    S_AXI_WVALID : in std_logic;
    S_AXI_WREADY : out std_logic;
    S_AXI_BRESP : out std_logic_vector(1 downto 0);
    S_AXI_BVALID : out std_logic;
    S_AXI_BREADY : in std_logic;
    S_AXI_ARADDR : in std_logic_vector(31 downto 0);
    S_AXI_ARVALID : in std_logic;
    S_AXI_ARREADY : out std_logic;
    S_AXI_RDATA : out std_logic_vector(31 downto 0);
    S_AXI_RRESP : out std_logic_vector(1 downto 0);
    S_AXI_RVALID : out std_logic;
    S_AXI_RREADY : in std_logic;
    AXI_STR_TXD_ACLK : in std_logic;
    AXI_STR_TXD_ARESETN : in std_logic;
    AXI_STR_TXD_TVALID : in std_logic;
    AXI_STR_TXD_TREADY : out std_logic;
    AXI_STR_TXD_TLAST : in std_logic;
    AXI_STR_TXD_TDATA : in std_logic_vector(31 downto 0);
    AXI_STR_RXD_ACLK : in std_logic;
    AXI_STR_RXD_ARESETN : in std_logic;
    AXI_STR_RXD_TVALID : out std_logic;
    AXI_STR_RXD_TREADY : in std_logic;
    AXI_STR_RXD_TLAST : out std_logic;
    AXI_STR_RXD_TDATA : out std_logic_vector(31 downto 0)
  );
end system_core1_0_wrapper;

architecture STRUCTURE of system_core1_0_wrapper is

  component core1 is
    generic (
      C_S_AXI_ADDR_WIDTH : INTEGER;
      C_S_AXI_DATA_WIDTH : INTEGER
    );
    port (
      S_AXI_ACLK : in std_logic;
      S_AXI_ARESETN : in std_logic;
      INTERRUPT : out std_logic;
      S_AXI_AWADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
      S_AXI_AWVALID : in std_logic;
      S_AXI_AWREADY : out std_logic;
      S_AXI_WDATA : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
      S_AXI_WSTRB : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
      S_AXI_WVALID : in std_logic;
      S_AXI_WREADY : out std_logic;
      S_AXI_BRESP : out std_logic_vector(1 downto 0);
      S_AXI_BVALID : out std_logic;
      S_AXI_BREADY : in std_logic;
      S_AXI_ARADDR : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
      S_AXI_ARVALID : in std_logic;
      S_AXI_ARREADY : out std_logic;
      S_AXI_RDATA : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
      S_AXI_RRESP : out std_logic_vector(1 downto 0);
      S_AXI_RVALID : out std_logic;
      S_AXI_RREADY : in std_logic;
      AXI_STR_TXD_ACLK : in std_logic;
      AXI_STR_TXD_ARESETN : in std_logic;
      AXI_STR_TXD_TVALID : in std_logic;
      AXI_STR_TXD_TREADY : out std_logic;
      AXI_STR_TXD_TLAST : in std_logic;
      AXI_STR_TXD_TDATA : in std_logic_vector(31 downto 0);
      AXI_STR_RXD_ACLK : in std_logic;
      AXI_STR_RXD_ARESETN : in std_logic;
      AXI_STR_RXD_TVALID : out std_logic;
      AXI_STR_RXD_TREADY : in std_logic;
      AXI_STR_RXD_TLAST : out std_logic;
      AXI_STR_RXD_TDATA : out std_logic_vector(31 downto 0)
    );
  end component;

begin

  core1_0 : core1
    generic map (
      C_S_AXI_ADDR_WIDTH => 32,
      C_S_AXI_DATA_WIDTH => 32
    )
    port map (
      S_AXI_ACLK => S_AXI_ACLK,
      S_AXI_ARESETN => S_AXI_ARESETN,
      INTERRUPT => INTERRUPT,
      S_AXI_AWADDR => S_AXI_AWADDR,
      S_AXI_AWVALID => S_AXI_AWVALID,
      S_AXI_AWREADY => S_AXI_AWREADY,
      S_AXI_WDATA => S_AXI_WDATA,
      S_AXI_WSTRB => S_AXI_WSTRB,
      S_AXI_WVALID => S_AXI_WVALID,
      S_AXI_WREADY => S_AXI_WREADY,
      S_AXI_BRESP => S_AXI_BRESP,
      S_AXI_BVALID => S_AXI_BVALID,
      S_AXI_BREADY => S_AXI_BREADY,
      S_AXI_ARADDR => S_AXI_ARADDR,
      S_AXI_ARVALID => S_AXI_ARVALID,
      S_AXI_ARREADY => S_AXI_ARREADY,
      S_AXI_RDATA => S_AXI_RDATA,
      S_AXI_RRESP => S_AXI_RRESP,
      S_AXI_RVALID => S_AXI_RVALID,
      S_AXI_RREADY => S_AXI_RREADY,
      AXI_STR_TXD_ACLK => AXI_STR_TXD_ACLK,
      AXI_STR_TXD_ARESETN => AXI_STR_TXD_ARESETN,
      AXI_STR_TXD_TVALID => AXI_STR_TXD_TVALID,
      AXI_STR_TXD_TREADY => AXI_STR_TXD_TREADY,
      AXI_STR_TXD_TLAST => AXI_STR_TXD_TLAST,
      AXI_STR_TXD_TDATA => AXI_STR_TXD_TDATA,
      AXI_STR_RXD_ACLK => AXI_STR_RXD_ACLK,
      AXI_STR_RXD_ARESETN => AXI_STR_RXD_ARESETN,
      AXI_STR_RXD_TVALID => AXI_STR_RXD_TVALID,
      AXI_STR_RXD_TREADY => AXI_STR_RXD_TREADY,
      AXI_STR_RXD_TLAST => AXI_STR_RXD_TLAST,
      AXI_STR_RXD_TDATA => AXI_STR_RXD_TDATA
    );

end architecture STRUCTURE;

